Memory cell

(canceled)

A method of fabricating a non volatile memory cell comprising a floating gate transistor comprising floating gate positioned between a control gate and a first channel region, and an access gate transistor comprising an access gate and a second channel region, the first channel region comprising a first implant having a first dosage level, and the second channel region comprising a second implant having a second dosage level, the first dosage level being less than the second dosage level, the method comprising the steps of implanting ions into a substrate at a first dosage level within the range of 0 to 5e11 cm−2;

• masking the substrate to form a masked part and an unmasked part;
• implanting further ions into the unmasked part to form a region in the substrate having a second dosage level of ions, the second dosage level being higher than the first dosage level to thereby form first and second implants.