Array architecture for embedded flash memory devices

A method of manufacturing memory devices, the method comprising:

• forming a well region in a substrate;
• forming a first polysilicon layer overlying the well region in the substrate;
• forming a dielectric layer overlying the first polysilicon layer;
• forming a second polysilicon layer overlying the dielectric layer to form a stack layer including the first polysilicon layer, dielectric layer, and second polysilicon layer;
• patterning the stack layer to simultaneously form a flash memory device and a select device, the flash memory device including a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of the first polysilicon layer, the select device including a second portion of the second polysilicon layer overlying a second portion of the dielectric layer overlying a second portion of the first polysilicon layer;
• and
• forming a connection between the second portion of the second polysilicon layer and the second portion of the first polysilicon layer for the select device, while maintaining isolation between the first portion of the second polysilicon layer and the first portion of the first polysilicon layer for the first flash memory device;
• whereupon the select device is configured to be activated by applying a voltage to the second portion of first polysilicon layer.