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US 2011/0298031 A1Published application
Semiconductor memory device including multi-layer gate structure
AssigneeKabushiki Kaisha Toshiba
InventorToshitake Yaegashi
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Abstract
A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.
Claims1
A semiconductor memory device comprising:
- a first select transistor formed on a side of an upper surface of a substrate and having a first multi-layer gate;
- a first stepped portion formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of said substrate;
- and
- a first contact plug formed in the first stepped portion.
1 more element
Dependencies are inferred from the claim text.