Semiconductor storage device
AssigneeUnisantis Electronics (Japan) Ltd.
InventorsFujio MASUOKA, Shintaro Arai
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Abstract
In a 4F2 memory cell designed using an SGT as a vertical transistor, a bit line has a high resistance because it is comprised of a diffusion layer underneath a pillar-shaped silicon layer, which causes a problem of slowdown in memory operation speed. The present invention provides a semiconductor storage device comprising an SGT-based 4F2 memory cell, wherein a bit line-backing cell having the same structure as that of a memory cell is inserted into a memory cell array to allow a first bit line composed of a diffusion layer to be backed with a low-resistance second bit line through the bit line backing cell, so as to provide a substantially low-resistance bit line, while suppressing an increase in area of the memory cell array.
Claims6
A semiconductor storage device comprising:
- a memory cell array formed using a vertical transistor which has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to a pillar-shaped semiconductor layer and a gate electrode surrounds the pillar-shaped semiconductor layer;
- first bit lines formed by a first layer, said first bit lines being wired in a row direction so that each first bit line is connected to a sense amplifier;
- second bit lines formed by a second layer, said second bit lines being wired in the row direction so that each second bit line is connected to a sense amplifier;
- and
- a plurality of vertical transistors and a plurality of pillar-shaped semiconductor layers formed on each first bit line,
- wherein each vertical transistor is a first transistor for selecting a memory cell, and a gate electrode of the first transistor is connected to a corresponding one of word lines wired in a column direction,
- wherein a contact is formed on each pillar-shaped semiconductor layer,
- wherein each first bit line and a corresponding second bit line are connected to one another through a corresponding pillar-shaped semiconductor layer and the contact formed on the corresponding pillar-shaped semiconductor layer.
Dependencies are inferred from the claim text.