Semiconductor device

A semiconductor device comprising:

• a plurality of memory cells, each of the plurality of memory cells comprising:
• a first transistor;
• a second transistor having a portion which overlaps with the first transistor;
• an insulating film over a part of the first transistor, and
• a capacitor,
• wherein the first transistor comprises:
• a first channel formation region,
• a first gate insulating layer provided over the first channel formation region,
• a first gate electrode provided over the first gate insulating layer so as to overlap with the first channel formation region, and
• a first source electrode and a first drain electrode electrically connected to the first channel formation region,
• wherein the second transistor comprises:
• a second channel formation region over the insulating film,
• a second source electrode and a second drain electrode electrically connected to the second channel formation region,
• a second gate electrode provided so as to overlap with the second channel formation region, and
• a second gate insulating layer provided between the second channel formation region and the second gate electrode,
• wherein the first gate electrode is surrounded by the insulating film and the insulating film does not cover a top surface of the first gate electrode,
• wherein the second source electrode is formed of a material having etching selectivity with respect to the first gate electrode, and the second source electrode is provided on and in contact with the top surface of the first gate electrode, and
• wherein the first gate electrode, the second source electrode, and one electrode of the capacitor are electrically connected to each other.

A semiconductor device comprising:

• a first transistor;
• a second transistor having a portion which overlaps with the first transistor;
• an insulating film over a part of the first transistor;
• and
• a capacitor,
• wherein the first transistor comprises:
• a first channel formation region,
• a first gate insulating layer provided over the first channel formation region,
• a first gate electrode provided over the first gate insulating layer so as to overlap with the first channel formation region, and
• a first source electrode and a first drain electrode electrically connected to the first channel formation region,
• wherein the second transistor comprises:
• a second channel formation region over the insulating film,
• a second source electrode and a second drain electrode electrically connected to the second channel formation region,
• a second gate electrode provided so as to overlap with the second channel formation region, and
• a second gate insulating layer provided between the second channel formation region and the second gate electrode,
• wherein the first gate electrode is surrounded by the insulating film and the insulating film does not cover a top surface of the first gate electrode,
• wherein the second source electrode is formed of a material having etching selectivity with respect to the first gate electrode, and the second source electrode is provided on and in contact with the top surface of the first gate electrode, and
• wherein the second gate insulating layer is sandwiched between a first electrode of the capacitor and a second electrode of the capacitor, wherein the second electrode of the capacitor is the second source electrode.

A semiconductor device comprising:

• a plurality of memory cells, each of the plurality of memory cells comprising:
• a first transistor;
• a second transistor having a portion which overlaps with the first transistor;
• an insulating film over a part of the first transistor;
• and
• a capacitor,
• wherein the first transistor comprises:
• a first channel formation region,
• a first gate insulating layer provided over the first channel formation region,
• a first gate electrode provided over the first gate insulating layer so as to overlap with the first channel formation region, and
• a first source electrode and a first drain electrode electrically connected to the first channel formation region,
• wherein the second transistor comprises:
• a semiconductor layer comprising a second channel formation region over the insulating film,
• a second source electrode and a second drain electrode electrically connected to the second channel formation region,
• a second gate electrode provided so as to overlap with the second channel formation region, and
• a second gate insulating layer provided between the second channel formation region and the second gate electrode,
• wherein the first gate electrode is surrounded by the insulating film and the insulating film does not cover a top surface of the first gate electrode,
• wherein the second source electrode is formed of a material having etching selectivity with respect to the first gate electrode, and the second source electrode is provided on and in contact with the top surface of the first gate electrode, and
• wherein the semiconductor layer and the second gate insulating layer are sandwiched between a first electrode of the capacitor and a second electrode of the capacitor, wherein the second electrode of the capacitor is the second source electrode.

A method of manufacturing a semiconductor device comprising the steps of:

• forming a first channel formation region in a semiconductor substrate;
• forming a first source region and a first drain region in the semiconductor substrate so that the first channel formation region is sandwiched between the first source region and the first drain region;
• forming a first gate insulating layer over the first channel formation region;
• forming a first gate electrode over the first gate insulating layer;
• forming an insulating film over the first source region and the first drain region;
• wherein the first gate electrode is surrounded by the insulating film and the insulating film does not cover a top surface of the first gate electrode;
• forming a second channel formation region over the insulating film;
• and
• forming a second source electrode on and in contact with the top surface of the first gate electrode and electrically connected to the second channel formation region,
• wherein the second source electrode comprises a material having etching selectivity with respect to the first gate electrode.