Organic light emitting diode display and method for manufacturing the same

A method of manufacturing an organic light emitting diode (OLED) display, comprising:

• preparing a substrate main body;
• sequentially layering a polycrystalline silicon layer, a gate insulating layer and a first metal layer on the substrate main body;
• forming a polycrystalline silicon layer pattern, a gate insulating layer pattern and a first conductive layer pattern by patterning the polycrystalline silicon layer, the gate insulating layer and the first metal layer;
• forming an interlayer insulating layer pattern on the first conductive layer pattern;
• and
• forming a second conductive layer pattern on the interlayer insulating layer pattern,
• wherein the polycrystalline silicon layer pattern includes the polycrystalline active layer and the first capacitor electrode,
• wherein the gate insulating layer pattern has a plurality of contact holes exposing a portion of the polycrystalline silicon layer pattern and is formed in a same pattern as the polycrystalline silicon layer pattern, and
• wherein the first conductive layer pattern includes the gate electrode and the second capacitor electrode that are formed on the gate insulating layer pattern.

A method of manufacturing an organic light emitting diode (OLED) display, comprising:

• preparing a substrate main body;
• sequentially layering a polycrystalline silicon layer, a gate insulating layer, a doped amorphous silicon layer and a first metal layer on the substrate main body;
• forming the polycrystalline silicon layer pattern that includes the polycrystalline active layer and the first capacitor electrode;
• forming a gate insulating layer intermediate formed on the polycrystalline silicon layer pattern;
• forming a first conductive layer intermediate formed on the gate insulating layer intermediate by patterning the polycrystalline silicon layer, the gate insulating layer, the doped amorphous silicon layer and the first metal layer together;
• forming an interlayer insulating layer on the first conductive layer intermediate;
• forming a first conductive layer pattern and an interlayer insulating layer pattern exposing a portion of the gate insulating layer intermediate by patterning the first conductive layer intermediate and the interlayer insulating layer;
• forming a gate insulating layer pattern exposing a portion of the polycrystalline active layer by etching the gate insulating layer intermediate exposed through the first conductive layer pattern and the interlayer insulating layer pattern;
• and
• forming a second conductive layer pattern on the polycrystalline active layer and the interlayer insulating layer pattern.