Thin film transistor array substrate and manufacturing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorDong-Gyu KIM
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Abstract
A thin film transistor array substrate includes a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an upper film thicker than the lower film, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer formed on the semiconductor layer, a data line electrically connected to a source electrode and a drain electrode formed on the ohmic contact layer, the lower film of the gate line is in contact with the gate insulating layer at a crossing portion of the gate line and the data line and the heights of the source electrode and the drain electrode are substantially the same as or less than a height of the semiconductor layer.
Claims23
A thin film transistor array substrate comprising:
- a gate line disposed on a substrate, the gate line comprising a gate electrode;
- a gate insulating layer formed on the gate line;
- a semiconductor layer formed on the gate insulating layer;
- and
- a source electrode and a drain electrode formed on the semiconductor layer, and a data line electrically connected to the source electrode, the data line crossing the gate line at a crossing portion,
- wherein the gate line at the crossing portion is thinner than the gate electrode.
A method of manufacturing a thin film transistor array substrate, the method comprising:
- forming a gate line disposed on a substrate, the gate line comprising a gate electrode;
- forming a gate insulating layer over the gate electrode;
- forming a semiconductor layer over the gate insulating layer;
- forming an ohmic contact layer over the semiconductor layer;
- forming a data layer over the ohmic contact layer;
- depositing a photoresist layer on the data layer;
- forming a data line, a source electrode, and a drain electrode using the photoresist as a mask;
- and
- removing the photoresist on the source electrode and the drain electrode, wherein the gate line at a crossing portion of the gate line and the data line is thinner than the gate electrode.
Dependencies are inferred from the claim text.