Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKiyoshi KATO
Life of this patent
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Abstract
An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the gate insulating layer and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.
Claims22
A semiconductor device comprising:
- a semiconductor layer comprising a channel formation region;
- a source region and a drain region electrically connected to the channel formation region;
- a gate electrode overlapping with the channel formation region;
- and
- a gate insulating layer between the semiconductor layer and the gate electrode,
- wherein a portion of a side surface of the gate insulating layer and a portion of a side surface of the source region or the drain region are substantially aligned with each other.
A semiconductor device comprising:
- a channel formation region provided in a substrate;
- a gate insulating layer over the channel formation region;
- a gate electrode over the gate insulating layer, the gate electrode overlapping with the channel formation region;
- and
- a source region and a drain region between which the channel formation region is sandwiched,
- wherein a portion of a side surface of the channel formation region and a portion of a side surface of the gate insulating layer are substantially aligned with each other.
A semiconductor device comprising:
- a first transistor comprising:
- a first channel formation region provided in a substrate;
- a first gate insulating layer over the first channel formation region;
- a first gate electrode over the first gate insulating layer, the first gate electrode overlapping with the first channel formation region;
- and
- a first source region and a first drain region between which the first channel formation region is sandwiched;
- and
- a second transistor comprising:
- a semiconductor layer comprising a second channel formation region;
- a second source region and a second drain region electrically connected to the second channel formation region;
- a second gate electrode overlapping with the second channel formation region;
- and
- a second gate insulating layer between the second channel formation region and the second gate electrode,
- wherein the first channel formation region and the second channel formation region comprise different semiconductor materials as respective main components, and
- wherein a portion of a side surface of the second gate insulating layer and a portion of a side surface of the second source region or the second drain region are substantially aligned with each other.
Dependencies are inferred from the claim text.