# US 2011/0297931 A1 · Method of fabricating a thin film transistor array substrate

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- Number: US 2011/0297931 A1
- Document ID: US20110297931A1
- Status: Published application
- Kind: A1
- Application number: 13/210,282
- Filed: 2011-08-15
- Published: 2011-12-08
- Earliest claimed: 2008-12-30
- Assignees: Samsung Display Co., Ltd.
- Inventors: Dong-Ju YANG; Yu-Gwang JEONG; Ki-Yeup LEE; Sang-Gab KIM; Yun-Jong YEO; Shin-Il CHOI; Hong-Kee CHIN; Seung-Ha CHOI; Jung-Suk BANG
- Web page: https://patentgrep.com/patent/US20110297931A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

## Claims

### Claim at position 1

1-13. (canceled)

### Claim 14

A thin film transistor (TFT) array substrate, comprising;
a gate interconnection line comprising a gate line and a gate electrode arranged on an insulating substrate;
a gate insulating layer arranged on the gate interconnection line;
a semiconductor layer arranged on the gate insulating layer;
a data interconnection line comprising a data line, a source electrode, and a drain electrode arranged on the semiconductor layer;
a first passivation layer arranged on the data interconnection line and exposing a portion of the drain electrode;
a pixel electrode electrically connected to the drain electrode, and formed on the first passivation layer corresponding to the transmission area of the display area.

### Claim 15 (depends on 14)

The TFT array substrate of claim 14, wherein the semiconductor layer includes an oxide semiconductor including at least one of Hafnium, Zinc, Indium, Gallium, and Tin.

### Claim 16 (depends on 14)

The TFT array substrate of claim 14, wherein the first passivation film comprises silicon oxide or silicon oxy-nitride.

### Claim 17 (depends on 14)

The TFT array substrate of claim 14, wherein the gate insulating layer is patterned exposing a portion of the pad area, and does not contact the pixel electrode in the transmission area of the display area.