US 2011/0297928 A1Published application

Semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsAtsuo ISOBE, Yoshinori IEDA, Keitaro IMAI, Kiyoshi KATO, Yuto YAKUBO, Yuki HATA

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Abstract

The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

Claims11

Dependent claims

A semiconductor device comprising:

a first memory cell comprising a first transistor and a second transistor, the first transistor and the second transistor overlapping with each other at least partly;
and
a second memory cell comprising a third transistor and a fourth transistor, the third transistor and the fourth transistor overlapping with each other at least partly,
wherein each of the first transistor and the third transistor comprises:
a first source region;
a first drain region;
a first channel formation region between the first source region and the first drain region, the first channel formation region comprising a first semiconductor material;
and
a first gate electrode over the first channel formation region with a first gate insulating layer interposed between the first gate electrode and the first channel formation region,
wherein each of the second transistor and the fourth transistor comprises:
a second channel formation region comprising a second semiconductor material different from the first semiconductor material;
a source electrode electrically connected to the second channel formation region;
a drain electrode electrically connected to the second channel formation region;
and
a second gate electrode over the second channel formation region with a second gate insulating layer interposed between the second gate electrode and the second channel formation region,
wherein the first source region or the first drain region is electrically connected to the source electrode or the drain electrode via a first conductive layer, and
wherein the source electrode or the drain electrode of the second transistor is electrically connected to the source electrode or the drain electrode of the fourth transistor via a wiring.

14 more elements

A semiconductor device comprising:

a first memory cell comprising a first transistor and a second transistor over the first transistor;
and
a second memory cell comprising a third transistor and a fourth transistor over the third transistor,
wherein each of the first transistor and the third transistor comprises:
a first channel formation region on an insulating surface;
an impurity region on the insulating surface;
and
a first gate electrode over the first channel formation region with a first gate insulating layer interposed between the first gate electrode and the first channel formation region,
wherein each of the second transistor and the fourth transistor comprises:
an oxide semiconductor layer comprising a second channel formation region;
and
a second gate electrode over the second channel formation region with a second gate insulating layer interposed between the second gate electrode and the second channel formation region,
wherein each of the first memory cell and the second memory cell further comprises:
a first electrode electrically connected to the oxide semiconductor layer;
a second electrode electrically connected to the oxide semiconductor layer;
a first conductive layer electrically connected to the impurity region;
and
a second conductive layer over the second gate insulating layer, the second conductive layer overlapping with the first electrode,
wherein the first electrode is in contact with a top face of the first gate electrode,
wherein the second electrode is in contact with a top face of the first conductive layer, and
wherein the second electrode of the first memory cell is electrically connected to the second electrode of the second memory cell via a wiring.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/117,588Filed 27 May 2011
Priority: JP 2010-1292784 Jun 2010
Published: 8 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H10B 41/70
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: the floating gate being an electrode shared by two or more…
H10D 86/423
Having a particular composition, shape or crystalline structure of the active layer: comprising semiconductor materials not belonging to the Group…
H10B 12/00
Dynamic random access memory [dram] devices