US 2011/0276731 A1 · DUAL-PORT FUNCTIONALITY FOR A SINGLE-PORT CELL MEMORY DEVICE

Abstract

A network node (5) including a line card (20) for packet-based data communications is disclosed. The line card (20) includes a transmit FIFO buffer (24T) and a receive FIFO buffer (24R), for buffering communications within the line card (20). Each of the buffers (24T, 24R) operate in a dual-port fashion, receiving asynchronous read and write requests, for reading data words from and writing data words to the buffers (24T, 24R). The buffers (24T, 24R) each include a memory array (45) of conventional single port random access memory cells, for example static RAM cells. Clock cycles are assigned by the buffers (24T, 24R) as internal read and internal write cycles, in alternating fashion. A write buffer (42) receives input data words, and schedules a double-data-word write to the memory array (45) upon receiving a pair of input data words, in the next internal write cycle. A read request buffer (44) receives read strobes, or read enable signals, from a downstream function, and upon receiving two such strobes, schedules the read of a double-data-word from the memory array (45). By converting the asynchronous read and write requests into scheduled reads and writes, respectively, the buffers (24T, 24R) operate as dual-port FIFO buffers.

Claims22

Dependent claims

A first-in-first-out memory, comprising:

a memory array having an array of single port memory cells;
a clock terminal that receives a clock signal;
a write enable terminal that receives a write enable signal;
inputs that receives input data words;
a read enable terminal that receives a read enable signal;
outputs that presents output data words of the same word width as that of the input data words;
a write buffer that is coupled to the inputs and to the array of memory cells, that receives a sequence of first and second input data words from the inputs in combination with corresponding write enable signals at the write enable terminal, wherein the write buffer performs a first width conversion of the first and second input data words to the memory array in a single write cycle;
read circuitry that requests a read of the memory array responsive to receiving first and second read enable signals at the read enable terminal;
and
a read buffer that receives first and second output data words from the memory array responsive to the request of the read of the memory array, and that presents the first and second output data words in sequence to the outputs.

7 more elements

A method of buffering data words with a memory circuit having an array of single port memory cells, the method comprising the steps of:

receiving a sequence of input data words at input terminals of the memory circuit;
responsive to receiving a first input data word and a second input data word, performing a first width conversion of the first and second input data words into a memory array of the memory circuit in a single write cycle;
receiving read strobe signals;
responsive to receiving first and second read strobe signals, reading first and second output data words from the memory array in a single read cycle;
performing a second width conversion of the first and second output data words;
and
sequentially presenting the first and second output data words at output terminals of the memory circuit, wherein the first and second output data words are of the same word_width as that of the input data words.

4 more elements

Dependencies are inferred from the claim text.

Dual-port functionality for a single-port cell memory device

Life of this patent

Dual-port functionality for a single-port cell memory device

Life of this patent

Abstract

Claims22