Clock distribution circuit and layout design method using the same

A layout design method for a clock tree circuit, comprising:

• disposing a first clock distribution circuit in a clock tree circuit;
• wiring the clock tree circuit in which the first clock distribution circuit is disposed;
• verifying timing of the wired clock tree circuit;
• and
• replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification,
• wherein each of the first and second clock distribution circuits comprises a first inverter circuit that receives an input signal, the first inverter circuit comprising:
• serially-connected N transistors having a first conductive type (N is a natural number equal to or greater than 2);
• and
• M transistors having a second conductive type (M is a natural number equal to or greater than 1), the M transistors being connected in series with the N transistors having the first conductive type, and
• wherein the first inventor of the first clock distribution circuit is different from the first inverter of the second clock distribution circuit in a combination of a pair of a transistor having the first conductive type and a transistor having the second conductive type, a control terminal of each of the pair of transistors receiving the input signal.