Overlapping error correction operations
AssigneeSanDisk IL Ltd.
InventorMenahem Lasser
Life of this patent
Estimating the term…
Abstract
Systems and methods of overlapping error correction operations are disclosed. A method at an encoder device includes receiving data bits to be encoded including a first bit, a second bit, and a third bit. A first encode operation to encode a first group of the data bits is initiated to generate a first codeword. The first group of the data bits includes the first bit and the second bit, but not the third bit. A second encode operation to encode a second group of the data bits is initiated to generate a second codeword. The second group of the data bits includes the second bit and the third bit, but not the first bit.
Claims34
A method of encoding data, the method comprising:
- at an encoder device coupled to a memory, the memory including a first portion and a second portion, wherein the first portion and the second portion overlap at a common portion:
- receiving data bits to be encoded, the data bits including at least a first bit, a second bit, and a third bit;
- initiating a first encode operation to encode a first group of the data bits to generate a first codeword, the first group including the first bit and the second bit, but not the third bit;
- and
- initiating a second encode operation to encode a second group of the data bits to generate a second codeword, the second group including the second bit and the third bit, but not the first bit;
- storing the first codeword and the second codeword to the memory, wherein storing the first codeword and the second codeword to the memory comprises:
- writing the first bit to a first location within the first portion, wherein the first location is not within the common portion;
- writing the second bit to a second location within the common portion;
- and
- writing the third bit to a third location within the second portion, wherein the third location is not within the common portion.
-5. (canceled)
A method comprising:
- at a decoder device that is coupled to receive data corresponding to data bits that have been encoded, the data bits including a first bit, a second bit, and a third bit, wherein a first codeword encodes a first group of the data bits, the first group of the data bits including the first bit and the second bit, but not the third bit, and wherein a second codeword encodes a second group of the data bits, the second group of the data bits including the second bit and the third bit, but not the first bit:
- receiving first data that corresponds to the first codeword and second data that corresponds to the second codeword;
- initiating a second decode operation to decode the second data, wherein the second decode operation is initiated in response to a prior decode operation failing to decode the first data due to errors in the first data;
- and
- initiating a first decode operation to decode the first data after decoding the second data.
A device comprising:
- an encoder configured to receive data bits including a first bit, a second bit, and a third bit from a data source and to:
- initiate a first encode operation at the encoder to encode a first group of the data bits to generate a first codeword, the first group including the first bit and the second bit, but not the third bit;
- and
- initiate a second encode operation at the encoder to encode a second group of the data bits to generate a second codeword, the second group including the second bit and the third bit, but not the first bits
- a memory having a first portion and a second portion, wherein the first portion and the second portion include a common portion;
- and
- a controller coupled to the memory and to the encoder, wherein the controller is configured to:
- send the first bit to a first location within the first portion, wherein the first location is not within the common portion;
- send the second bit to a second location within the common portion;
- and
- send the third bit to a third location within the second portion, wherein the third location is not within the common portion.
(canceled)
(canceled)
A device comprising:
- a decoder coupled to receive data corresponding to data bits that have been encoded, the data bits including a first bit, a second bit, and a third bit, wherein a first codeword encodes a first group of the data bits, the first group of the data bits including the first bit and the second bit, but not the third bit, and wherein a second codeword encodes a second group of the data bits, the second group of the data bits including the second bit and the third bit, but not the first bit, wherein the decoder is configured to:
- receive first data that corresponds to the first codeword and second data that corresponds to the second codeword;
- initiate a second decode operation to decode the second data, wherein the second decode operation is initiated in response to a prior decode operation failing to decode the first data due to errors in the first data;
- and
- initiate a first decode operation to decode the first data after decoding the second data.
Dependencies are inferred from the claim text.