Method and apparatus for ac scan testing with distributed capture and shift logic
AssigneeAdvanced Micro Devices, Inc.
InventorsAmitava Majumdar, Vasu Ganti
Life of this patent
Estimating the term…
Abstract
An integrated circuit device includes a plurality of functional tiles. Each functional tile may be configured into a scan chain. A clock generator is operable to generate an internal clock signal that is distributed to each of the functional tiles. A clock gater is associated with each of the functional tiles. Each clock gater is operable to receive an external enable signal and the internal clock signal, generate a scan clock signal for loading a test pattern into the scan chain based on the external enable signal and the internal clock signal, and generate at least one capture clock signal for capturing a response of the tile to the test pattern responsive to identifying the loading of the test pattern.
Claims30
An integrated circuit device, comprising:
- a plurality of functional tiles, wherein each functional tile may be configured into a scan chain;
- a clock generator operable to generate an internal clock signal that is distributed to each of the functional tiles;
- and
- a clock gater associated with each of the functional tiles, each clock gater being operable to receive an external enable signal and the internal clock signal, generate a scan clock signal for loading a test pattern into the scan chain based on the external enable signal and the internal clock signal, and generate at least one capture clock signal for capturing a response of the tile to the test pattern responsive to identifying the loading of the test pattern.
A method for testing an integrated circuit device including a plurality of functional tiles, comprising:
- configuring storage elements in a particular functional tiles into scan chains;
- generating an internal clock signal in the integrated circuit device and distributing the internal clock signal to each of the functional tiles;
- receiving an external enable signal and the internal clock signal at each functional tile;
- generating a scan clock signal for loading a test pattern into at least one of the scan chains based on the external enable signal and the internal clock signal;
- and
- generating at least one capture clock signal for capturing a response of the at least one functional tile to the test pattern responsive to identifying the loading of the test pattern.
An integrated circuit device including a plurality of functional tiles configurable as scan chains, comprising:
- means for generating an internal clock signal in the integrated circuit device and distributing the internal dock signal to each of the functional tiles;
- means for receiving an external enable signal and the internal clock signal at each functional tile;
- means for generating a scan clock signal for loading a test pattern into at least one of the scan chains based on the external enable signal and the internal clock signal;
- and
- means for generating at least one capture clock signal for capturing a response of the at least one functional tile to the test pattern responsive to identifying the loading of the test pattern.
Dependencies are inferred from the claim text.