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US 2011/0258502 A1Published application
Wafer scale testing using a 2 signal jtag interface
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
Claims3
An integrated circuit die, comprising:
- A. channel circuitry having a channel interface that includes a bidirectional data input/output lead carrying a test mode select signal, a test data in signal, and a test data out signal, and a clock input lead, and a linking module interface that includes a test mode select output lead, a test data in output lead, a test data out input lead, and a test clock output lead;
- B. TAP domains, each TAP domain being connected to combinational logic and having a TAP interface that includes a test mode select input, a test data input, a test clock input, and a test data output;
- and
- C. TAP linking module circuitry having a first interface connected to the linking module interface of the channel circuitry and second interfaces, each second interface being connected to the TAP interface of a TAP domain.
1 more element
Dependencies are inferred from the claim text.