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AssigneeSytest Technologies, Inc.
InventorsNur A. TOUBA, Laung-Terng WANG, Zhigang JIANG, Shianling WU, Jiangping YAN
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A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
An apparatus having compressed scan inputs that accept compressed scan patterns for generating decompressed scan patterns to test a scan-based integrated circuit, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, said apparatus characterized by a programmable pipelined decompressor comprising:
A method that accepts a compressed scan pattern stored in an ATE (automatic test equipment) for generating a decompressed scan pattern in a decompressor for testing a scan-based integrated circuit, said decompressor accepting the compressed scan patterns via compressed scan inputs for generating the decompressed scan patterns, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the decompressor, the decompressor comprising one or more programmable shift registers connected to said compressed scan inputs and a combinational logic network connected to said compressed scan inputs and said shift register outputs for connecting the outputs of said combinational logic network to selected scan inputs of all said scan chains, said method comprising:
A method that accepts a compressed scan pattern stored in an ATE (automatic test equipment) for generating a decompressed scan pattern in a decompressor to test a scan-based integrated circuit, said decompressor accepting the compressed scan patterns via compressed scan inputs for generating the decompressed scan patterns, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the decompressor, the decompressor comprising one or more shift registers connected to said compressed scan inputs and a combinational logic network connected to said compressed scan inputs and said shift register outputs for connecting the outputs of said combinational logic network to selected scan inputs of all said scan chains, said method comprising:
A method for automatically generating a compressed scan pattern at the compressed scan inputs of a decompressor to test a scan-based integrated circuit connected to the decompressor, the scan-based integrated circuit containing multiple scan chains, each scan chain comprising multiple scan cells coupled in series, the scan chains coupled to the decompressor, the decompressor comprising one or more programmable shift registers connected to said compressed scan inputs and a combinational logic network connected to said compressed scan inputs and said shift register outputs for connecting the outputs of said combinational logic network to selected scan inputs of all said scan chains, the compressed scan inputs receiving said compressed scan pattern from an automatic test equipment (ATE) and generating a decompressed scan pattern for driving the scan inputs of said multiple scan chains embedded in the scan-based integrated circuit, said method comprising:
Dependencies are inferred from the claim text.