System for performing the test of digital circuits
AssigneeSTMicroelectronics S.r.l.
InventorMarco Casarsa
Life of this patent
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Abstract
A system performs the test of a digital circuit. The system comprises a controller configured for executing the test of the digital circuit, a memory configured for storing a status of the digital circuit, and a state machine configured for controlling, before the execution of the test, the storage into the memory of the status of the digital circuit and configured for controlling, after the execution of the test, the restore into the digital circuit of the status stored into the memory.
Claims16
A system for performing a test of a digital circuit, the system comprising:
- a controller configured to execute the test of the digital circuit;
- a memory configured to store a status of the digital circuit;
- and
- a state machine configured to:
- control storing into the memory the status of the digital circuit, before the test is executed;
- control restoring into the digital circuit, after the test is executed, the status stored into the memory.
An integrated circuit comprising:
- a digital circuit including:
- at least one output test terminal configured to provide at least one output test signal carrying a status of the digital circuit or carrying data calculated according to a logic function implemented by the digital circuit;
- and
- at least one input test data terminal;
- an application module configured to generate a signal for activating a test of the digital circuit;
- a controller configured to execute the test of the digital circuit;
- a memory configured to store the status of the digital circuit;
- and
- a state machine configured to:
- control storing into the memory the status of the digital circuit, before the test is executed;
- control restoring the stored status into the digital circuit via the at least one input test data terminal after the test is executed.
A method for performing a test of a digital circuit, comprising:
- generating at least one first signal for controlling storing into a memory of a status of the digital circuit;
- storing the status of the digital circuit into the memory;
- executing the test of the digital circuit after storing the status of the digital circuit into the memory;
- generating at least one second signal for controlling restoring into the digital circuit of the status stored into the memory;
- and
- after executing the test of the digital circuit, restoring into the digital circuit the status stored into the memory.
A non-transitory computer-readable medium comprising instructions configured to cause a processor to implement a method that includes:
- generating at least one first signal for controlling storing into a memory of a status of a digital circuit;
- storing the status of the digital circuit into the memory;
- executing a test of the digital circuit after storing the status of the digital circuit into the memory;
- generating at least one second signal for controlling restoring into the digital circuit of the status stored into the memory;
- and
- after executing the test of the digital circuit, restoring into the digital circuit the status stored into the memory.
Dependencies are inferred from the claim text.