Test Architecture Including Cyclical Cache Chains, Selective Bypass Scan Chain Segments, And Blocking Circuitry
AssigneeSynopsys, Inc.
InventorsAnshuman Chandra, Jyotirmoy Saikia, Rohit Kapur
Life of this patent
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Abstract
A test architecture is described that adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values.
Claims12
A test architecture for testing of an integrated circuit design, the test architecture comprising:
- a plurality of scan chains;
- a plurality of cyclical cache chains;
- a decompressor for receiving scan inputs and mapping the scan inputs to the plurality of scan chains and the plurality of cyclical cache chains;
- a compressor for receiving outputs of the plurality of scan chains and the plurality of cyclical cache chains, and generating scan outputs;
- inverting logic for inverting one or more values from the cyclical cache chains, the inverting logic generating a subset of the scan inputs for the decompressor;
- and
- control logic for selecting between a linear mode and a cyclical mode,
- wherein in the linear mode, only top level scan inputs are mapped to the scan chains, and
- wherein in the cyclical mode, outputs of the plurality of cyclical cache chains and top level scan inputs are mapped to the scan chains.
A test architecture for testing of an integrated circuit design, the test architecture comprising:
- a plurality of scan chains;
- a decompressor for receiving scan inputs and mapping the scan inputs to the plurality of scan chains;
- a compressor for receiving outputs of the plurality of scan chains and generating scan outputs,
- wherein at least one scan chain includes a first segment, a second segment, and a multiplexer for receiving outputs of the first and second segments and allowing selective bypass of the second segment.
A test architecture for testing of an integrated circuit design, the test architecture comprising:
- a plurality of scan chains;
- a decompressor for receiving scan inputs and mapping the scan inputs to the plurality of scan chains;
- blocking circuitry for programmably blocking one or more outputs of the plurality of scan chains;
- and
- a compressor for receiving outputs of the blocking circuitry and generating scan outputs.
A computer-readable medium comprising computer instructions that, when run on a computer, perform steps for testing of an integrated circuit design, the steps comprising:
- receiving scan inputs and mapping the scan inputs to a plurality of scan chains and a plurality of cyclical cache chains;
- receiving first outputs of the plurality of scan chains and second outputs of the plurality of cyclical cache chains, and generating scan outputs from the first and second outputs;
- inverting one or more values from the cyclical cache chains, the inverting values being a subset of the scan inputs;
- and
- selecting between a linear mode and a cyclical mode,
- wherein in the linear mode, only top level scan inputs are mapped to the scan chains, and
- wherein in the cyclical mode, outputs of the plurality of cyclical cache chains and top level scan inputs are mapped to the scan chains.
A computer-readable medium comprising computer instructions that, when run on a computer, perform steps for testing of an integrated circuit design, the steps comprising:
- receiving scan inputs and mapping the scan inputs to a plurality of scan chains, wherein at least one scan chain includes a first segment and a second segment;
- receiving first outputs of the plurality of scan chains and generating scan outputs from the first outputs,
- wherein receiving the first outputs includes receiving outputs of the first and second segments and allowing selective bypass of the second segment.
A computer-readable medium comprising computer instructions that, when run on a computer, perform steps for testing of an integrated circuit design, the steps comprising:
- receiving scan inputs and mapping the scan inputs to the plurality of scan chains;
- programmably blocking one or more outputs of the plurality of scan chains;
- and
- receiving outputs of the scan chains after blocking and generating scan outputs.
Dependencies are inferred from the claim text.