Dynamically Calibrated DDR Memory Controller
AssigneeUniquify, Inc.
InventorsJung Lee, Mahesh Goplan
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Abstract
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided.
Claims7
A DDR memory controller for read operations, comprising:
- a dqs clock driven by a DDR memory;
- a core clock originating within the DDR memory controller;
- a dqs delay element producing a delayed dqs;
- a dq read data register clocked by the delayed dqs;
- a core clock delay element that produces a capture clock;
- a first core domain register responsive to said dq read data register and clocked by said capture clock;
- a second core domain register responsive to said first core domain register and clocked by the core clock;
- a dynamically self-configuring logic circuit responsive to said read data register and said first and second core domain registers, for controlling said core clock delay element;
- and
- wherein the delay of the core clock delay element is set using said self-configuring logic circuit by a calibration procedure completed during operation of the DDR memory controller
A method for calibrating a DDR memory controller during dynamic operation to provide an optimum delay for a core clock delay element to produce an optimum capture clock signal, comprising the steps of:
- issuing a sequence of read commands so that a delayed version of a dqs signal toggles continuously;
- delaying a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal, whereby this core clock delay is recorded as “A”;
- delaying the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal, whereby this core clock delay is recorded as “B”;
- computing an optimum delay “C” for the core clock signal to produce a capture clock signal using the formula:
- if B−A>A then C=(A+B)/2, otherwise C=A/2.
A method for calibrating a DDR memory controller during dynamic operation to provide optimum CAS latency compensation, comprising the steps of:
- setting the delay for a core clock signal to a previously determined value that produces an optimum delay for a capture clock signal;
- reading a known data pattern previously saved or located in a DDR memory connected to a device containing the DDR memory controller;
- iteratively capturing read data from the DDR memory at different pre-determined CAS latency compensation values from a minimum to a maximum CAS latency compensation value;
- when the read data matches at a specific CAS latency compensation value, recording the specific CAS latency compensation value as the optimum CAS latency compensation value;
- and
- programming delay element values within the DDR memory controller that produced the optimum CAS latency compensation into control registers in the DDR memory controller.
Dependencies are inferred from the claim text.