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US 2011/0258469 A1Published application
Power reduction for system on chip
AssigneeIntel Corporation
InventorsTeck Ee Guan, Kai Hoong Fong
Life of this patent
Estimating the term…
Abstract
Disclosed herein are SOC devices with peripheral units having power management logic.
Claims20
A system-on-a-chip integrated circuit, comprising:
- a processor core;
- a peripheral unit communicatively coupled to said core, the peripheral unit comprising power management logic to determine when the peripheral may go into a power reduction state and to request entry into the power reduction state.
A method, comprising:
- within an SOC, receiving a power reduction request from a peripheral unit generated by power management logic within the peripheral unit;
- and
- sending a signal to cause power consumption in the peripheral to be reduced in response to the request.
A wireless communications device, comprising:
- an SOC comprising a processor core, a peripheral unit communicatively coupled to said core, the peripheral unit having power management logic to determine when the peripheral may go into a power reduction state and to request entry into the power reduction state;
- an antenna coupled to the processor core through a wireless interface;
- and
- a serial communications interface coupled to the processor core through the peripheral unit.
1 more element
Dependencies are inferred from the claim text.