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US 2011/0258418 A1Published application
Load/Move Duplicate Instructions for a Processor
AssigneeIntel Corporation
InventorPatrice Roussel
Life of this patent
Estimating the term…
Abstract
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.
Claims20
1-58. (canceled)
An apparatus comprising:
- a front end to receive an instruction indicating a source and a destination, the source having a first plurality of packed floating point values, the first plurality of the packed floating point values including a first floating point value, a second floating point value, and a third floating point value, the second floating point value between the first floating point value and the third floating point value;
- and
- an execution core coupled with the front end, the execution core to store a result corresponding to the instruction in the destination, the result including a second plurality of packed floating point values, the second plurality of the packed floating point values including a fourth floating point value that is equal to the first floating point value, a fifth floating point value that is equal to the first floating point value, a sixth floating point value that is equal to the third floating point value, and a seventh floating point value that is equal to the third floating point value,
- wherein the instruction implicitly indicates that the fourth and fifth floating point values are to be equal to the first floating point value.
1 more element
An apparatus comprising:
- a front end to receive an instruction indicating a single source and a destination, the source including a first plurality of packed single precision floating point values, the first plurality of the packed single precision floating point values including a first single precision floating point value in bits [31-0] of the source, a second single precision floating point value in bits [63-32] of the source, a third single precision floating point value in bits [95-64] of the source, and a fourth single precision floating point value in bits [127-96] of the source;
- and
- an execution core coupled with the front end, the execution core to store a packed result corresponding to the instruction in the destination indicated by the instruction, the packed result including a second plurality of packed single precision floating point values, the second plurality of the packed single precision floating point values including a fifth single precision floating point value in bits [31-0] of the packed result that is equal to the first single precision floating point value, a sixth single precision floating point value in bits [63-32] of the packed result that is equal to the first single precision floating point value, a seventh single precision floating point value in bits [95-64] of the packed result that is equal to the third single precision floating point value, and an eighth single precision floating point value in bits [127-96] of the packed result that is equal to the third single precision floating point value.
An apparatus comprising:
- a front end to receive an instruction indicating a single source and a destination, the source including a first plurality of packed single precision floating point values, the first plurality of the packed single precision floating point values including a first single precision floating point value in bits [31-0] of the source, a second single precision floating point value in bits [63-32] of the source, a third single precision floating point value in bits [95-64] of the source, and a fourth single precision floating point value in bits [127-96] of the source;
- and
- an execution core coupled with the front end, the execution core to store a packed result corresponding to the instruction in the destination indicated by the instruction, the packed result including a second plurality of packed single precision floating point values, the second plurality of the packed single precision floating point values including a fifth single precision floating point value in bits [31-0] of the packed result that is equal to the second single precision floating point value, a sixth single precision floating point value in bits [63-32] of the packed result that is equal to the second single precision floating point value, a seventh single precision floating point value in bits [95-64] of the packed result that is equal to the fourth single precision floating point value, and an eighth single precision floating point value in bits [127-96] of the packed result that is equal to the fourth single precision floating point value.
An apparatus comprising:
- a front end to receive instructions including a first instruction and a second instruction, the first instruction indicating a single first source and a first destination, the second instruction indicating a single second source and a second destination, the first instruction a different type of instruction than the second instruction;
- and
- an execution core coupled with the front end, the execution core to store a first packed result corresponding to the first instruction and to store a second packed result corresponding to the second instruction, the first packed result including bits [31-0] of the first source stored in bits [63-32] and [31-0] of the first destination, and bits [95-64] of the first source stored in bits [127-96] and [95-64] of the first destination, the second packed result including bits [63-32] of the second source stored in bits [31-0] and [63-32] of the second destination and bits [127-96] of the second source stored in bits [95-64] and [127-96] of the second destination.
Dependencies are inferred from the claim text.