Preventing Fast Read Before Write in Static Random Access Memory Arrays

A processor comprising:

• a controller;
• and
• a cache access memory coupled to the controller, wherein the cache access memory comprises:
• first circuitry for determining whether a memory access for a memory cell in a plurality of memory cells in the cache access memory is either a read operation or a write-through operation, for determining whether a data input signal is in a first state or a second state in response to determining the memory access as the write-through operation, and for outputting a global write line signal in the first state in response to the data input signal being in the second state;
• second circuitry for outputting a column select signal in the second state in response to the global write line signal being in the first state;
• and
• third circuitry for keeping a downstream read path of the cache access memory at the first state such that data output by the cache access memory is in the first state in response to the column select signal being in the second state.

An information handling system comprising:

• a processor;
• and
• memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to:
• determine, using first circuitry in the cache access memory, whether a memory access for a memory cell in a plurality of memory cells in the cache access memory is either a read operation or a write-through operation;
• responsive to determining the memory access as the write-through operation, determine, using the first circuitry, whether a data input signal is in a first state or a second state;
• responsive to the data input signal being in the second state, output, using the first circuitry, a global write line signal in the first state;
• responsive to the global write line signal being in the first state, output, using second circuitry, a column select signal in the second state;
• and
• responsive to the column select signal being in the second state, keep, using third circuitry, a downstream read path of the cache access memory at the first state such that data output by the cache access memory is in the first state.