Configurable memory device
AssigneeChip Memory Technology, Inc.
InventorWingyu Leung
Life of this patent
Estimating the term…
Abstract
A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.
Claims28
A method comprising:
- forming a memory device through providing an array of non-volatile memory cells including at least one non-volatile memory cell and an array of volatile memory cells including at least one volatile memory cell on a substrate;
- and
- appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device,
- wherein the address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.
A configurable memory device comprising:
- a substrate;
- an array of non-volatile memory cells including at least one non-volatile memory cell on the substrate;
- an array of volatile memory cells including at least one volatile memory cell on the substrate;
- and
- an interface configured to enable coupling of the memory device to a memory controller associated therewith, the interface comprising an address translation logic configured to be programmed through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device.
A computing system comprising:
- a memory device comprising:
- a substrate;
- an array of non-volatile memory cells including at least one non-volatile memory cell on the substrate;
- an array of volatile memory cells including at least one volatile memory cell on the substrate;
- and
- an interface comprising an address translation logic configured to be programmed through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in the computing system;
- and
- a memory controller, associated with the memory device and coupled to the memory device through the interface.
Dependencies are inferred from the claim text.