Petaflops router

A PetaFlops Router that performs operations on at least one external data input vector comprising:

• a PetaFlops Router Node comprised of a Field Programmable Gate Array (FPGA), an intra-FPGA crossbar switch, and a plurality of input vector registers, each of said plurality of input vector registers being capable of simultaneously reading and writing, said FPGA configured to include a plurality of physical operators, said plurality of physical operators performing desired arithmetic and logic operations, said FPGA connected to said intra-FPGA crossbar switch, said intra-FPGA crossbar switch being programmable to configure how data is routed into and out of said plurality of physical operators making up said FPGA, including configuring intermediate computations on said at least one external data input vector by routing an output of a first physical operator of said plurality of physical operators of said FPGA into an input of a second physical operator of said plurality of physical operators of said FPGA to create intermediate computation input vectors to said intra-FPGA crossbar switch, said at least one external data input vector connected to said intra-FPGA crossbar switch via an input vector register selected from said plurality of vector registers, said intermediate computation input vectors connected to said intra-FPGA crossbar switch via additional input vector registers selected from said plurality of input vector registers such that there is an additional input vector register for each intermediate computation input;
• a manager system connected to said intra-FPGA crossbar switch such that said manager system manages operation of said intra-FPGA crossbar switch;
• said manager system having an instruction receiving subsystem that receives desired operation instructions for said PetaFlops Node, an instruction analysis subsystem that analyzes said desired operation instructions for said PetaFlops Router Node to determine which physical operators of said plurality of physical operators of said FPGA are capable of performing said operation instructions, an instruction assignment subsystem that assigns said desired operation instructions for said PetaFlops Router Node to said physical operators of said plurality of physical operators of said FPGA determined to be capable of performing said desired operation instructions for said PetaFlops Router Node, and a crossbar setup subsystem that sets up said intra-FPGA crossbar switch to route said at least one external data input vector and said intermediate computation input vectors in accord with said assignments of said desired operation instructions for said PetaFlops Router Node to said plurality of physical operators of said FPGA such that said desired operation instructions for said PetaFlops Router Node are executed;
• and
• wherein said PetaFlops Router Node further comprises a result delivery subsystem that delivers at least one final result data output data vector externally to a desired location, said at least one final result data output data vector produced based on said at least one external data input vector that receives data from an external data source via performance of operations on said at least one external data input vector in said physical operators of said FPGA in accord with said set up of said intra-FPGA crossbar switch.