Bus Arbitration Techniques to Reduce Access Latency
AssigneeQUALCOMM Incorporated
InventorFeng Wang
Life of this patent
Estimating the term…
Abstract
A method of arbitrating requests from bus masters for access to shared memory in order to reduce access latency, comprises looking ahead into currently scheduled requests to the shared memory and predicting latency of the requests based on characteristics of the currently scheduled requests, such as increasing page hit rate, or balancing read and write traffic. The requests are scheduled based at least in part on the predicted latency.
Claims21
A method of arbitrating requests from bus masters for access to shared memory in a processing system comprising:
- looking ahead into currently scheduled accesses to the shared memory;
- predicting latency of the requests from bus masters based on a characteristic of the currently scheduled accesses;
- and
- scheduling the requests from bus masters based at least in part on the predicted latency.
A processing system comprising:
- a shared memory system;
- bus masters configured to generate future requests to access the shared memory system;
- memory controllers configured to service currently scheduled requests;
- latency predictors configured to predict latency based on a characteristic of currently scheduled requests by the memory controller;
- and
- arbiters configured to select at least a subset of the future requests based at least in part on the predicted latency.
A processing system for arbitrating requests from bus masters for access to shared memory comprising:
- means for looking ahead into currently scheduled accesses to the shared memory;
- means for predicting latency of the requests from bus masters based on a characteristic of the currently scheduled accesses;
- and
- means for scheduling the requests from bus masters based at least in part on the predicted latency.
A method of arbitrating requests from bus masters for access to shared memory in a processing system comprising:
- step for looking ahead into currently scheduled accesses to the shared memory;
- step for predicting latency of the requests from bus masters based on a characteristic of the currently scheduled accesses;
- and
- step for scheduling the requests from bus masters based at least in part on the predicted latency.
Dependencies are inferred from the claim text.