US 2011/0257955 A1 · Gate-Level Logic Simulator Using Multiple Processor Architectures

Abstract

Techniques for simulating operation of a connectivity level description of an integrated circuit design are provided, for example, to simulate logic elements expressed through a netlist description. The techniques utilize a host processor selectively partitioning and optimizing the descriptions of the integrated circuit design for efficient simulation on a parallel processor, more particularly a SIMD processor. The description may be segmented into cluster groups, for example macro-gates, formed of logic elements, where the cluster groups are sized for parallel simulation on the parallel processor. Simulation may occur in an oblivious as well as event-driven manner, depending on the implementation.

Claims39

Dependent claims

A method for logic simulation of a connectivity level description of an integrated circuit, where the connectivity level description comprises a plurality of logic elements, the method comprising:

in a first processor, clustering logic elements into cluster groups each comprising at least one of the plurality of logic elements, where the cluster groups are sized such that, during a simulation cycle, each cluster group is capable of being simulated on a different processor block of a second processor, wherein the processing units of the second processor are capable of simultaneous operation;
and
in the second processor, simultaneously simulating a plurality of the cluster groups each being simulated on a different one of the processing units.

Dependencies are inferred from the claim text.

Gate-Level Logic Simulator Using Multiple Processor Architectures

Life of this patent

Gate-Level Logic Simulator Using Multiple Processor Architectures

Life of this patent

Abstract

Claims39