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US 2011/0257943 A1Published application
Node-based transient acceleration method for simulating circuits with latency
AssigneeTexas Instruments Incorporated
InventorGang Peter Fang
Life of this patent
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Abstract
When modeling a circuit, transient analysis is an important part of the analysis. However, for transient analyses, device model evaluating can consume a considerable amount of time, when using conventional simulators. Here, a simulator is provided that allows for detection of latency on a node-by-node basis, as opposed to a device-by-device basis with conventional simulators. Using this type of analysis can greatly reduce the time of an analysis, which affects both the cost of a product and its time to market.
Claims14
A method comprising:
- receiving a product specification for a circuit having a plurality of active devices that are coupled to one another through a plurality of nodes;
- generating a matrix representation of a system of equations that is generally representative of the circuit, wherein the matrix representation has a plurality of matrix rows, and wherein each matrix row corresponds to at least one of the nodes;
- iteratively solving the matrix representation of the system of equations for each of a plurality of transient time points to generate a simulation of the circuit, wherein the step of iteratively solving includes the substeps of:
- determining if each node satisfies a latency condition for each iteration of each transient time point;
- and
- using a previous iteration for each matrix row when each of its nodes satisfies the latency condition.
3 more elements
A processor having a computer program product embodied thereon, the computer program product comprising:
- computer code for receiving a product specification for a circuit having a plurality of active devices that are coupled to one another through a plurality of nodes;
- computer code for generating a matrix representation of a system of equations that is generally representative of the circuit, wherein the matrix representation has a plurality of matrix rows, and wherein each matrix row corresponds to at least one of the nodes;
- computer code for iteratively solving the matrix representation of the system of equations for each of a plurality of transient time points to generate a simulation of the circuit, wherein the step of iteratively solving includes the substeps of:
- computer code for determining if each node satisfies a latency condition for each iteration of each transient time point;
- and
- computer code for using a previous iteration for each matrix row when each of its nodes satisfies the latency condition.
3 more elements
An apparatus comprising:
- a storage medium having a matrix solver, a device evaluator, a latency detector, a convergence checker, and a matrix loader stored thereon, and
- a processor having an engine embodied thereon that is in communication with the storage medium, wherein the engine:
- receives a product specification for a circuit having a plurality of active devices that are coupled to one another through a plurality of nodes;
- generates, with the matrix loader and the device evaluator, a matrix representation of a system of equations that is generally representative of the circuit, wherein the matrix representation has a plurality of matrix rows, and wherein each matrix row corresponds to at least one of the nodes;
- iteratively solves, with the matrix solver, the matrix loader, the latency detector, ad the convergence checker, the matrix representation of the system of equations for each of a plurality of transient time points to generate a simulation of the circuit, wherein the engine iteratively solves by:
- determining with the latency detector if each node satisfies a latency condition for each iteration of each transient time point;
- and
- using a previous iteration with the matrix loader for each matrix row when each of its nodes satisfies the latency condition.
5 more elements
Dependencies are inferred from the claim text.