Method for detecting variance in semiconductor processes
AssigneeInotera Memories, Inc.
InventorsYIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN
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Abstract
A method of detecting variance by regression model has the following steps. Step 1 is preparing the FDC data and WAT data for analysis. Step 2 is figuring out what latent variable effect of WAT data by Factor Analysis Step 3 is utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components. Step 4 is demonstrating how the tools and FDC data affect WAT data by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.
Claims20
A method for detecting variation in semiconductor processes, comprising the following steps:
- collecting a plurality of tool process data, a plurality of first raw data and a plurality of second raw data respectively by process tools, a WAT (Wafer Acceptance Test) system and a FDC (Fault Detection and Classification) system;
- pre-processing said first raw data and said second raw data by an operation management unit;
- using a first statistic analysis method to process said first raw data to reduce said first raw data and calculate a plurality of correlation data by a feature extract device;
- using a second statistic analysis method to process said second raw data to locate a plurality of global index data representing said second raw data by a latent variable extract device;
- using a third statistic analysis method to process the plurality of tool process data, the plurality of global index data and the plurality of correlation data to build a plurality of interrelationship indices by a variance detect device;
- and
- locating the essential reason causing such a semiconductor process variation based on the plurality of interrelationship indices by the operation management unit.
A method for detecting variance in semiconductor processes, comprising the following steps:
- collecting a plurality of tool process data, a plurality of first raw data and a plurality of second raw data respectively by process tools, a WAT (Wafer Acceptance Test) system and a FDC (Fault Detection and Classification) system;
- pre-processing the plurality of first raw data and the plurality of second raw data by an operation management unit;
- processing the plurality of first raw data by using Factor Analysis (FA) to simplify the plurality of first raw data and calculate the plurality of correlation data by a feature extract device;
- processing the plurality of second raw data by using Principal Component Analysis (PCA) to locate the plurality of global index data representing the plurality of second raw data by a latent variable extract device;
- processing the tool process data, the global index data and the correlation data by using Analysis of Covariance (ANCOVA) to build a plurality of interrelationship indices by a variance detect device;
- locating the essential reason causing the semiconductor process variation based on the plurality of interrelationship indices by the operation management unit.
Dependencies are inferred from the claim text.