Nand flash memory array with cut-off gate line and methods for operating and fabricating the same

A method for fabricating a NAND flash memory array comprising:

• a first step of carrying out an ion injection process for forming a source or drain region in a prepared silicon substrate;
• a second step of coating a photoresist on the substrate and patterning the photoresist in a direction of bit line;
• a third step of forming silicon fins by using the each photoresist pattern as a mask and etching a silicon in the substrate;
• a fourth step of depositing an insulating material on a whole surface of the substrate, and etching the insulating material to be left only between the silicon fins;
• a fifth step of coating a photoresist on the upper part of the substrate and patterning the photoresist in a direction of word line;
• a sixth step of forming a plurality of trenches by using the each photoresist pattern as a mask, etching the exposed silicon fins and the exposed insulating material one after the other;
• a seventh step of forming a first oxide layer on a whole surface of the substrate or on the exposed silicon surface;
• an eighth step of forming a plurality of cut-off gate lines by depositing metal or silicon-like material on a whole surface of the substrate and etching the metal or silicon-like material to be left only in portion of the low part of the each trench;
• a ninth step of leaving the first oxide layer only in both sides and low part of the cut-off gate line by removing the first oxide layer exposed by etching the metal or silicon-like material;
• a tenth step of forming a second oxide layer on a whole surface of the substrate, the exposed silicon surface, or the exposed silicon-like material surface;
• an eleventh step of forming a charge storage layer on each side wall by depositing a charge trap dielectric layer on a whole surface of the substrate and etching the charge trap dielectric layer anisotropically;
• and
• a twelfth step of forming a plurality of word lines by depositing a third oxide layer on a whole surface of the substrate, further depositing metal or silicon-like material on a whole surface of the substrate, and etching the metal or silicon-like material to be left only in the each trench.