Novel poly resistor and poly efuse design for replacement gate technology

A method comprising:

• forming an isolation region on a substrate having a substrate surface, wherein the isolation region has an isolation region surface that is in a plane lower than the substrate surface;
• thereafter, forming a first gate structure over the substrate surface and a second gate structure over the isolation region surface, wherein the first gate structure and the second gate structure include a hard mask layer;
• thereafter, removing the hard mask layer from the second gate structure;
• thereafter, forming a source region and a drain region in the substrate, wherein the first gate structure interposes the source region and the drain region;
• thereafter, forming a protection layer over the second gate structure;
• thereafter, forming a silicide feature on the source region and the drain region;
• thereafter, removing the hard mask layer from the first gate structure.

A method comprising:

• providing a semiconductor substrate;
• forming a shallow trench isolation in the semiconductor substrate;
• etching the shallow trench isolation such that the shallow trench isolation has a concave surface that is in a plane lower than a surface of the semiconductor substrate;
• forming a resistive structure over the concave surface of the shallow trench isolation;
• and
• performing a salicidation process, wherein the resistive structure is protected during the salicidation process.