Methods of Manufacturing a Semiconductor Device

A method of manufacturing a semiconductor device, comprising:

• providing a substrate divided into at least an NMOS forming region and a PMOS forming region;
• forming a gate insulating layer on the substrate by depositing a metal oxide compound having a dielectricity higher than silicon nitride;
• forming a polysilicon layer and a hard mask layer over the gate insulating layer;
• patterning the hard mask layer and etching the polysilicon layer to form integrated structures of a polysilicon pattern and a hard mask pattern;
• forming impurity doped regions in the substrate on both sides of the integrated structures;
• and
• forming a first preliminary insulating interlayer covering the integrated structures as a composite layer of two or more layers by forming a first insulating material layer with good gap-filling properties and forming thereon a second insulating material layer having a small deposition thickness variation, wherein the upper surface of the first preliminary insulating layer is higher than an upper surface of the integrated structures.

A method of manufacturing a semiconductor device, comprising:

• forming integrated structures of polysilicon patterns and hard mask patterns on a substrate;
• forming a first preliminary insulating interlayer on the integrated structures, an upper surface of the first preliminary insulating interlayer being higher than an upper surface of the hard mask patterns;
• performing a first polishing of the first preliminary insulating interlayer until at least one upper surface of the hard mask patterns is exposed, forming a second preliminary insulating interlayer, wherein the first polishing comprises:
• using a first slurry to polish the first preliminary insulating interlayer to a predetermined thickness without exposing the upper surface of the hard mask patterns;
• and
• using a second slurry having a slower polishing rate than the first slurry to polish the first preliminary insulating interlayer until at least one upper surface of the hard mask patterns is exposed,
• wherein after performing the first polishing, a distance variation from a surface of the substrate to an upper surface of the second preliminary insulating interlayer is less than a thickness variation of the hard mask pattern