US 2011/0255652 A1 · SHIFT REGISTER

Abstract

An exemplary shift register includes a control circuit and an output circuit. The control circuit is electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal. A logic low level of the first clock pulse signal is lower than a level of the power supply voltage. The output circuit is subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal. The second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.

Claims9

Dependent claims

A shift register comprising:

a control circuit, electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal, wherein a logic low level of the first clock pulse signal is lower than a level of the power supply voltage;
and
an output circuit, subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal, wherein the second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.

A shift register comprising:

a control circuit, having a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal and comprising:
a first control transistor, wherein the gate of the first control transistor is electrically coupled to the first clock pulse signal input terminal, the source/drain of the first control transistor is electrically coupled to the power supply voltage input terminal, and the drain/source of the first control transistor is electrically coupled to the gate of the first control transistor through a coupling capacitor;
and
a second control transistor, wherein the gate of the second control transistor is electrically coupled to the first clock pulse signal input terminal, the source/drain of the second control transistor is electrically coupled to the drain/source of the first control transistor, and the drain/source of the second control transistor is electrically coupled to the start pulse signal input terminal;
and
a first output transistor, wherein the gate of the first output transistor is electrically coupled to the drain/source of the first control transistor, the source/drain of the first output transistor serves as a gate driving signal output terminal, the drain/source of the first output transistor serves as a second clock pulse signal input terminal;
wherein the first control transistor, the second control transistor and the first output transistor all are negative threshold voltage transistors.

4 more elements

Dependencies are inferred from the claim text.

Shift register

Life of this patent

Shift register

Life of this patent

Abstract

Claims9