Digital Second-Order CDR Circuits

A method for performing a clock and data recovery, the method comprising:

• providing data and a clock;
• in a first finite state machine (FSM) cycle, generating a second-order phase code from accumulated first-order phase codes, wherein the accumulated first-order phase codes are generated by accumulating first first-order phase codes in FSM cycles earlier in time than the first FSM cycle;
• in a second FSM cycle after the first FSM cycle, determining a first-order phase code by comparing the data and the clock;
• generating a plurality of candidate total phase codes from the second-order phase code;
• and
• performing a multiplexing to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code, wherein the multiplexing is controlled by the first-order phase code.

A method for performing a clock and data recovery, the method comprising:

• providing data and a clock;
• in a first finite state machine (FSM) cycle, accumulating first-order phase codes retrieved from different FSM cycles to generate a second-order phase code, wherein the second-order phase code is a non-integer value;
• generating a group of second-order phase codes having an average equal to the non-integer value;
• assigning the group of second-order phase codes as second-order phase codes of a group of consecutive FSM cycles, wherein the group of consecutive FSM cycles is later in time than the first FSM cycle;
• in each of the consecutive FSM cycles, determining a first-order phase code;
• and
• in each of the consecutive FSM cycles, generating a total phase code equal to a sum of the first-order phase code and a respective one of the group of second-order phase codes for each of the group of consecutive FSM cycles.

A clock and data recovery circuit comprising:

• a finite state machine (FSM) comprising:
• an early/late determination circuit configured to output a first-order phase code;
• a second-order accumulator configured to receive and accumulate first-order phase codes for different FSM cycles, and to generate a second-order phase code;
• a step generator configured to generate a plurality of candidate total phase codes from the second-order phase code;
• and
• a multiplexer configured to receive the plurality of candidate total phase codes, wherein the multiplexer is controlled by the first-order phase code to output one of the plurality of candidate total phase codes as a total phase code.