US 2011/0255355 A1 · Leakage and NBTI Reduction Technique for Memory

Abstract

In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.

Claims20

Dependent claims

An integrated circuit comprising:

a plurality of memory cells coupled to a pair of bit lines, wherein the plurality of memory cells are powered by a first power supply voltage during use;
a circuit coupled to the pair of bit lines and powered by the first power supply voltage during use, wherein the circuit is coupled to receive a first control signal, and wherein the circuit is configured to maintain a precharge voltage on one bit line of the pair of bit lines responsive the other one of the pair of bit lines being discharged during use and further responsive to a first logic level on the first control signal, and wherein the circuit is disabled responsive to a second level on the first control signal;
and
a power control unit configured to generate the first control signal, wherein the power control unit is configured to assert the second level on the first control signal responsive to the determining that a second power supply voltage to other circuitry in the integrated circuit is being powered down.

1 more element

Dependencies are inferred from the claim text.

Leakage and NBTI Reduction Technique for Memory

Life of this patent

Leakage and NBTI Reduction Technique for Memory

Life of this patent

Abstract

Claims20