Semiconductor memory

A semiconductor memory, comprising:

• a plurality of nonvolatile memory cells including cell transistors each including a control gate and a floating gate;
• a plurality of bit lines coupled to the respective cell transistors;
• a word line commonly coupled to the control gate;
• a plurality of selection switches coupled to the respective bit lines, and coupling the bit lines to a common node;
• a precharge switch coupling the common node to a precharge line;
• a sense amplifier determining logic of data which is read from each of the nonvolatile memory cells to the common node via each of the bit lines;
• a reset switch coupling the common node to a ground line;
• and
• an operation control circuit which, in a read operation, turns off at least one of selection switches corresponding to at least one of the nonvolatile memory cells from which data is not read, among all the selection switches being turned-on, and turns off the reset switch being turned-on, and temporarily turns on the precharge switch to activate the word line.

A semiconductor memory, comprising:

• a nonvolatile memory cell including a cell transistor including a control gate and a floating gate;
• a bit line coupled to the cell transistor;
• a word line coupled to the control gate;
• a sense amplifier determining logic of data read from the nonvolatile memory cell via the bit line;
• a global bit line coupled to the sense amplifier;
• and
• a sense amplifier enable switch coupling the sense amplifier to the global bit line in a read operation.