Sub volt flash memory system
AssigneeMicrochip Technology Incorporated
InventorsHieu Van Tran, Sang T. Nguyen, Anh Ly, Hung Q. Nguyen
Life of this patent
Estimating the term…
Abstract
Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
Claims10
A bitline sensing load circuit comprising:
- a diode connected MOS transistor including a first terminal for coupling to a first voltage supply, including a second terminal for coupling to a memory cell terminal and for providing a voltage indicative of the content stored in said memory cell, and further including a bulk voltage terminal, locally provided, for coupling to a second voltage supply, the second voltage supply having a voltage different from the first voltage supply and having a voltage different from ground;
- and
- a bipolar junction transistor including an emitter and a collector coupled between the memory cell terminal and a third supply voltage terminal and the memory cell terminal for applying a preemphasis voltage on the memory cell terminal before sensing a voltage on the memory cell terminal indicative of content of a memory cell coupled thereto.
A method for controlling a memory operation on a flash memory, the method comprising:
- applying a preemphasis signal on a signal line coupled to a plurality of memory cells, the preemphasis signal having at least one characteristic dependent on loading of the signal line.
Dependencies are inferred from the claim text.