Memory voltage cycle adjustment
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
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Abstract
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.
Claims22
A method of programming a memory cell with a programming signal, the programming signal comprises a plurality of programming pulses, wherein the programming pulses incrementally change by at least one step voltage, the method comprising:
- determining a quantity of processing cycles performed on a group of memory cells;
- and
- adjusting the at least one step voltage responsive to the determined quantity of processing cycles.
A method comprising;
- determining a quantity of processing cycles performed on a group of memory cells;
- and
- adjusting an initial programming pulse of a programming signal comprising a plurality of programming pulses from an initial program voltage to an adjusted voltage, in response to the determined number of processing cycles, wherein the plurality of programming pulses comprise a number of stepped voltage pulses having at least two different step voltages.
A memory device comprising;
- an array of memory cells;
- and
- control circuitry coupled to the array and configured to perform a method of programming a memory cell with a programming signal, the programming signal comprises a plurality of programming pulses, wherein the programming pulses incrementally change by at least one step voltage, the method comprising:
- determining a quantity of processing cycles performed on a group of memory cells;
- and
- adjusting the at least one step voltage responsive to the determined quantity of processing cycles.
A memory device comprising;
- an array of memory cells;
- and
- control circuitry coupled to the array and configured to:
- determine a quantity of processing cycles performed on a group of memory cells;
- and
- adjust an initial programming pulse of a programming signal comprising a plurality of programming pulses from an initial program voltage to an adjusted voltage, in response to the determined number of processing cycles, wherein the plurality of programming pulses comprise a number of stepped voltage pulses having at least two different step voltages.
Dependencies are inferred from the claim text.