Flash memory device and method of operation
AssigneeOcz Technology Group, Inc.
InventorFranz Michael Schuette
Life of this patent
Estimating the term…
Abstract
A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.
Claims14
A NAND flash memory device having a memory cell comprising a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge, and means for modulating the erase voltage according to the level of the programming charge on the floating gate.
A method of operating a NAND flash memory device having a memory cell comprising a floating gate, a control gate connected to a wordline to receive a control voltage therefrom and induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge, the method comprising decreasing the erase voltage if the control voltage is below a threshold level to avoid over-erasing of the floating gate.
Dependencies are inferred from the claim text.