Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells respectively having a gate connected to one of the word lines;
• a word line driver configured to drive voltages of the word lines;
• and
• a sense amplifier configured to detect data of the memory cells via the bit lines, wherein
• the memory cells are connected in series between one of the respective bit lines and a source to constitute a cell string,
• multiple bits of data is stored in a selected memory cell by performing a first writing stage and a second writing stage, the first writing stage brings the selected memory cell into a first state by repeating a writing loop comprising a write operation and a verify read operation, the write operation is an operation in which data is written in the selected memory cell in the cell string, the verify read operation is an operation in which it is verified that the data is written in the selected memory cell, the second writing stage brings the selected memory cell from the first state into a second state by repeating the writing loop, and
• the word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string during the verify read operation when the second writing stage is performed on the selected memory cell, the increased verification voltage is greater than the verification voltage when the first writing stage is performed on the selected memory cell.