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US 2011/0255334 A1Published application
Flash memory having multi-level architecture
AssigneeMicron Technology, Inc.
InventorsAlessandro Grossi, Giulio Albini, Anna Maria Conti
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Abstract
Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.
Claims20
A method of fabricating a memory device, the method comprising:
- forming peripheral circuitry on a substrate;
- covering said peripheral circuitry and said substrate with an interlayer dielectric layer;
- and
- forming a stack of one or more levels of memory arrays on said interlayer dielectric layer.
1 more element
The method of claim 3, further comprising:
- exposing said polysilicon thin film by removing a portion of said metal layer and said ONO stack to define parallel gate lines.
A memory device comprising:
- peripheral circuitry on a substrate;
- an interlayer dielectric layer to cover said peripheral circuitry;
- and
- one or more levels of memory arrays formed on said interlayer dielectric layer, wherein said peripheral circuitry is disposed between said substrate and said interlayer dielectric layer.
1 more element
A system comprising:
- a memory device comprising:
- peripheral circuitry on a substrate;
- an interlayer dielectric layer to cover said peripheral circuitry;
- and
- one or more levels of memory arrays on said interlayer dielectric layer;
- a memory controller to operate said memory device, and
- a processor to host one or more applications and to initiate write commands to said memory controller to provide access to memory cells in said memory arrays.
4 more elements
Dependencies are inferred from the claim text.