Phase change memory device with improved performance that minimizes cell degradation

A phase change memory device comprising:

• a cell array including a phase change resistor configured to read/write data;
• a plurality of sense amplifiers configured to compare multi-voltage levels of a reference voltage signal with a multi-voltage levels of a sensing voltage signal received from the cell array, wherein the sense amplifiers are connected to a global bit line through a global column switching unit;
• a plurality of write driving units configured to supply multi-voltage levels of a driving voltage signal corresponding to write data to the cell array;
• and
• a reference level selecting unit configured to select a multi-voltage levels of a read reference voltage signal in a read mode so as to output the reference voltage signal, and to select one voltage level of a multi-voltage levels of a set reference voltage signal when a input data is a set data and to select one voltage level of multi-voltage levels of a reset reference voltage signal when a input data if a reset data in a write verifying mode so as to output the one voltage level of the reference voltage signal;
• wherein the sense amplifiers includes:
• a sensing current voltage converting unit configured to convert a multi-level sensing current received from the cell array into the sensing voltage signal;
• an amplifier configured to compare and amplify the reference voltage signal with the sensing voltage signal;
• and
• a latch unit configured to latch an output signal of the amplifier.