Semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorTakashi SAKOH
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to the first bit line; a second memory cell connected to the second bit line; a first reference cell acting as the reference cell; a second reference cell acting as another reference cell; a potential line that supplies the reference potential to the first and second reference cells; and a dummy cell comprising a coupling capacitor that stabilizes potential of the potential line.
Claims12
A semiconductor memory device that reads data by comparing a potential of a memory cell with a reference potential of a reference cell, comprising:
- first and second bit lines connected to a same sense amplifier;
- a first memory cell connected to said first bit line;
- a second memory cell connected to said second bit line;
- a first reference cell connected to said first bit line;
- a second reference cell connected to said second bit line;
- a potential line that supplies said reference potential to said first and second reference cells;
- and
- a dummy cell provided in addition to said first and second reference cells and said first and second memory cells;
- said dummy cell comprising a coupling capacitor whose one end is electrically connected directly to said potential line.
A semiconductor memory device comprising:
- a comparing unit that compares a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell;
- first and second bit lines connected to inputs of said comparing unit;
- a first memory cell connected to said first bit line;
- a second memory cell connected to said second bit line;
- a first reference cell acting as said reference cell;
- a second reference cell acting as another reference cell;
- a potential line that supplies said reference potential to said first and second reference cells;
- and
- a dummy cell comprising a coupling capacitor that stabilizes potential of said potential line.
A process for reading data of a memory cell comprising:
- providing a semiconductor memory device comprising:
- first and second bit lines connected to a comparing unit;
- a first memory cell connected to said first bit line;
- a second memory cell connected to said second bit line;
- a first reference cell connected to said first bit line;
- a second reference cell connected to said second bit line;
- a potential line that supplies said reference potential to said first and second reference cells;
- a dummy cell comprising a coupling capacitor;
- comparing potential of a memory cell with a reference potential of a reference cell;
- wherein a potential of said coupling capacitor is directly supplied to said reference potential.
Dependencies are inferred from the claim text.