Semiconductor integrated circuit device capable of securing gate performance and channel length

A semiconductor integrated circuit device comprising:

• a semiconductor substrate divided into active regions and an isolation layer;
• a plurality of word lines extending parallel to one another and formed on the isolation layer of the semiconductor substrate;
• a plurality of bit lines extending parallel to one another on the semiconductor substrate, arranged to cross with the word lines, and delimiting a plurality of crossing regions where the word lines intersect the bit lines and a plurality of unit memory cell regions with each cell region bounded by an adjacent pair of the word lines and an adjacent pair of the bit lines;
• gate electrodes for the respective unit memory cell regions, and each gate electrode including a first portion which is electrically connected with any one of a pair of word lines which delimit a corresponding unit memory cell and a second portion which extends from one end of the first portion to overlap with any one of a pair of bit lines which delimit the corresponding unit memory cell;
• a plurality of storage node contacts respectively disposed in the unit memory cell regions;
• and
• a plurality of bit line contacts connecting the bit lines and the active regions,
• wherein shared gate contact parts, corresponding to portions of the word lines which are commonly contacted by the word lines and pairs of gate electrodes, and the bit line contacts are alternately arranged in a diagonal direction of the plurality of word lines and the plurality of bit lines.

A semiconductor integrated circuit device comprising:

• a semiconductor substrate including active regions;
• word lines arranged on the semiconductor substrate;
• bit lines arranged to cross with the word lines such that unit memory cells are each delimited by a pair of adjacent word lines and a pair of adjacent bit lines;
• gate electrodes contacting predetermined portions of the word lines and bent to overlap with the bit lines;
• and
• bit line contacts electrically connecting the bit lines and the active regions,
• wherein gate electrodes of unit memory cells, which adjoin each other with a word line interposed therebetween, are commonly connected with the corresponding word line, and
• wherein the bit line contacts are arranged on portions of the bit lines between an adjacent pair of the word lines.