Buffering deserialized pixel data in a graphics processor unit pipeline
AssigneeNVIDIA Corporation
InventorsTyson J. Bergland, Craig M. Okruhlica, Edward A. Hutchins, Michael J.M. Toksvig, Justin M. Mahan
Life of this patent
Estimating the term…
Abstract
An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
Claims20
A graphics pipeline in a graphics processor unit, the pipeline comprising:
- a plurality of arithmetic logic units (ALUs);
- a first buffer coupled to the plurality of ALUs, wherein each clock cycle the first buffer stores a subset of pixel data comprising one row of a series of rows of pixel data associated with a first plurality of pixels, and wherein after the first buffer accumulates all rows of pixel data for a pixel of the first plurality, then the pixel data for the pixel is available to be operated on by the plurality of ALUs;
- and
- a deserializer coupled to the first buffer and operable for deserializing the series of rows of pixel data before the pixel data is added to the first buffer.
A graphics pipeline in a graphics processor unit, the pipeline comprising:
- a data fetch stage having a first pipeline width measured in number of bits;
- and
- an arithmetic logic stage coupled to the data fetch stage and comprising:
- a plurality of arithmetic logic units (ALUs), wherein the arithmetic logic unit has a second pipeline width measured in number of bits, wherein the second pipeline width is greater than the first pipeline width;
- and
- a deserializer operable for deserializing rows of pixel data.
A computer-implemented method of processing pixel data in a graphics processor unit pipeline, the method comprising:
- deserializing serialized subsets of pixel data to produce a first plurality of deserialized pixel data, each of the subsets comprising one row of pixel data associated with a first plurality of pixels;
- storing the first plurality of deserialized pixel data for the first plurality of pixels in a first buffer;
- after all of the deserialized pixel data for a first pixel in the first plurality of pixels is received in the first buffer, performing arithmetic operations using the deserialized pixel data for the first pixel;
- and
- serializing the deserialized pixel data for the first pixel back into serialized subsets of pixel data after the arithmetic operations are performed.
Dependencies are inferred from the claim text.