Fast repeater latch

A circuit comprising:

• an output circuit having a first transistor and a second transistor and configured to drive an output signal onto an output node, wherein the first transistor is configured to drive the output signal when a first node is active, and wherein the second transistor is configured to drive the output signal when a second node is active;
• an input circuit coupled to the first node and the second node and further coupled to receive an input signal and a clock signal, wherein the input circuit is configured to activate the first node responsive to first logical transition of the input signal concurrent with a first state of the clock signal, and further configured to activate the second node responsive to a second logical transition of the input signal concurrent with the first state of the clock signal;
• a deactivation circuit configured to, independent of the clock signal, deactivate an active one of the first and second nodes at a delay time subsequent to activation of one of the first and second nodes;
• a latch having first and second inputs coupled to the first and second nodes, respectively, and configured to change a latch output state responsive to activation of one of the first and second nodes, and wherein the latch is further configured to maintain a state of the output signal subsequent to deactivation of the one of the first and second nodes.

An integrated circuit comprising:

• a first logic unit,
• a second logic unit,
• a signal path coupled between the first logic unit and the second logic unit, wherein the signal path includes one or more repeater circuits, wherein each of the one or more repeater circuits includes:
• an output circuit having a first transistor and a second transistor and configured to drive an output signal onto an output node, wherein the first transistor is configured to drive the output signal when a first node is active, and wherein the second transistor is configured to drive the output signal when a second node is active;
• an input circuit coupled to the first node and the second node and further coupled to receive an input signal and a clock signal, wherein the input circuit is configured to activate the first node responsive to first logical transition of the input signal concurrent with a first state of the clock signal, and further configured to activate the second node responsive to a second logical transition of the input signal concurrent with the first state of the clock signal;
• a deactivation circuit configured to, independent of the clock signal, deactivate an active one of the first and second nodes at a delay time subsequent to activation of one of the first and second nodes;
• a latch having first and second inputs coupled to the first and second nodes, respectively, and configured to change a latch output state responsive to activation of one of the first and second nodes, and wherein the latch is further configured to maintain a state of the output signal subsequent to deactivation of the one of the first and second nodes.