Pll frequency synthesizer

A PLL frequency synthesizer having a coarse-adjustment mode and a fine-adjustment mode, comprising:

• a voltage-controlled oscillator (VCO), having an inductor, a fine-adjustment capacitor, coupled between a control node and an oscillation node, whose capacitance value is continuously variable according to a voltage difference between the control node and the oscillation node, and a coarse-adjustment capacitor whose capacitance value can be switched in a stepwise fashion, the VCO being configured to generate an oscillation clock having an oscillation frequency depending on an inductance value of the inductor and on capacitance values of the fine-adjustment capacitor and the coarse-adjustment capacitor;
• a frequency divider configured to divide the frequency of the oscillation clock to generate a divided clock;
• a direct current (DC) voltage supply circuit configured to, in the coarse-adjustment mode, supply a DC voltage to the control node and change a voltage value of the DC voltage according to a DC value of an oscillation voltage at the oscillation node, and in the fine-adjustment mode, stop supplying the DC voltage;
• a frequency-band selection circuit configured to, in the coarse-adjustment mode, switch the capacitance value of the coarse-adjustment capacitor based on a frequency difference between a reference clock and the divided clock so that an oscillation frequency band of the VCO is set to an oscillation frequency band corresponding to a target frequency determined by a frequency of the reference clock and a division ratio of the frequency divider;
• and
• an oscillation control circuit configured to, in the fine-adjustment mode, increase or decrease a control voltage at the control node according to a phase difference between the reference clock and the divided clock.