Lockstep synchronization and maintenance
AssigneeXilinx, Inc.
InventorGlenn C. Steiner
Life of this patent
Estimating the term…
Abstract
A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and second circuits. A clock of the first circuit and/or second circuit is adjusted by an amount corresponding to the determined phase difference. In response to the phase difference being less than a threshold value, the first and second circuits are signaled to begin normal operation.
Claims20
A circuit for synchronizing a first processor and a second processor, comprising:
- a first phase comparator having a first input coupled to an output of the first processor and a second input coupled to an output of the second processor;
- a first phase-locked loop circuit having an input coupled to a clock source generator, an output coupled to a clock input of the first processor, and a control input coupled to an output of the phase comparator;
- and
- wherein the first phase comparator is configured to selectably operate in one of a first mode or a second mode;
- wherein, while operating in the first mode, the first phase comparator:
- determines a first phase difference between synchronization waveforms output from the first and second processors;
- outputs a signal indicative of the first phase difference to the control input of the first phase-locked loop circuit;
- and
- in response to the first phase difference being less than a selected value:
- outputs a signal to the first and second processors indicating the first and second processors are synchronized;
- and
- enters the second mode;
- and
- wherein, while operating in the second mode, the phase comparator:
- determines a second phase difference between signals received by the first and second inputs;
- and
- in response to the second phase difference being less than a selected value, outputs a signal to the first and second processors indicating the first and second processors are synchronized.
A system for synchronizing multiple circuits, comprising:
- a phase comparator;
- a first circuit having a plurality of outputs, including one or more outputs coupled to a first set of inputs of the phase comparator;
- a second circuit having a plurality of outputs, including one or more outputs coupled to a second set of inputs of the phase comparator;
- a timing adjustment circuit coupled to one or more inputs of the first circuit;
- wherein the phase comparator:
- determines a time-offset difference between the first set of inputs and the second set of inputs;
- and
- outputs the time-offset difference to the timing adjustment circuit;
- and
- wherein the timing adjustment circuit adjusts a signal output to the one or more inputs of the first circuit in response to the phase difference.
A method of synchronizing a first circuit and a second circuit, comprising
- signaling the first and second circuits to each generate respective waveform outputs;
- determining a phase difference between the generated waveform outputs from the first and second circuits;
- adjusting a clock signal of the first circuit by an amount corresponding to the determined phase difference;
- and
- in response to the phase difference being less than a threshold value, signaling the first and second circuits to begin normal operation.
Dependencies are inferred from the claim text.