Lock detector, method applicable thereto, and phase lock loop applying the same
AssigneeNovatek Microelectronics Corp.
InventorLiming Xiu
Life of this patent
Estimating the term…
Abstract
A lock detector for a phase lock loop (PLL) includes: first and second pulse width extenders, performing pulse width extension on first and second pulses for generating third and fourth pulses, respectively; first and second delay circuits, delaying the third and the fourth pulses into first and second sampling clocks, respectively; and a cross-sampling circuit, sampling the third pulse based on the second sampling clock and sampling the fourth pulse based on the first sampling clock to indicate whether the PLL is locked.
Claims15
A state detector applied in a phase lock loop, comprising:
- a first pulse width extender and a second pulse width extender for performing pulse extension on a first pulse and a second pulse to generate a third pulse and a fourth pulse, respectively;
- a first delay circuit and a second delay circuit for delaying the third pulse and the fourth pulse into a first sampling clock and a second sampling clock, respectively;
- and
- a cross-sampling circuit for sampling the third pulse according to the second sampling clock and for sampling the fourth pulse according to the first sampling clock to indicate whether the phase lock loop is in a lock state.
A phase lock loop comprising:
- a phase/frequency detector for comparing and detecting a reference clock and an output clock to output a first pulse and a second pulse;
- a lock detector coupled to the phase/frequency detector for sampling the second pulse according to the first pulse and for sampling the first pulse according to the second pulse to indicate whether the phase lock loop is locked;
- a charge pump coupled to the phase/frequency detector for converting the first and the second pulse into a control voltage;
- and
- a voltage controlled oscillator coupled to the charge pump for generating the output clock according to the control voltage.
A lock detecting method for detecting whether an output clock is locked to a reference clock, comprising:
- comparing and detecting the reference clock and the output clock to output a first pulse and a second pulse;
- extending a pulse width of the first pulse to generate a third pulse;
- extending a pulse width of the second pulse to generate a fourth pulse;
- delaying the third pulse into a first sampling clock;
- delaying the fourth pulse into a second sampling clock;
- and
- sampling the third pulse according to the second sampling clock and sampling the fourth pulse according to the first sampling clock to indicate whether the output clock is locked to the reference clock.
Dependencies are inferred from the claim text.