Fault-tolerant battery management system, circuits and methods

A fault tolerant battery management system comprising:

• a first set of electronic circuits and a second set of electronic circuits;
• each set for redundantly monitoring and managing a common plurality of interconnected battery cells;
• a controller for commanding and for collecting data from the first and second set of electronics;
• the first set of electronics constituted in slices of circuitry, each slice associated with and responsible for monitoring and managing one or more cells;
• further, any mode of the first set of circuits' that can interfere with the second set of circuits' monitoring and management of commonly connected cells requires at least two independent enables to be activated, at least one of the enables further requiring a coded message from the controller for activation;
• further, the controller, having notice of a failure in a slice of circuitry will effectively isolate that slice from interfering with its associated at least one cell.

A battery charging apparatus comprising:

• a) an electrical connection for a battery cell;
• b) a charge transfer circuit operationally coupled to the electrical connection, the circuit for transferring charge from, or optionally into, a connected cell;
• c) a mutually distinct first and second control logic circuit each having a respective enable signal as an output, both enable signals operatively coupled to said charge transfer circuit;
• the coupling of the enable signals to said charge transfer circuit such that activation of charge transfer requires both enable signals to contemporaneously be in activated states;
• further, the first and second control logic circuits being substantially constituted in mutually distinct fault domains.

A battery monitor and management apparatus for connecting to at least two cells comprising:

• a) at least one analog-to-digital converter having effectively at least two analog inputs;
• b) a stimulus circuit for applying known test conditions to the analog inputs;
• c) a first control circuit operatively coupled to said stimulus circuit, the control circuit constituted and arranged as to selectively enable application of the known test condition to the analog inputs;
• further, at least a portion of said stimulus circuit being comprised of electronic components situated in a fault domain other than that of the analog-to-digital converter;
• further,
• the stimulus circuit so configured as to provide a distinct stimulus to a first of the of the at least two analog inputs as compared to the stimulus provided to a distinct second of the at least two analog inputs;
• still further,
• when connected to the associated cells, the imposition of stimulus on the inputs has no significant hindering effect on the optional concurrent monitoring and managing of the connected cells by a second, duplicate redundant battery monitor and management apparatus, or optionally has provisions for fail-safe isolation to achieve non-interference.