Semiconductor Device and Method of Wafer Level Package Integration

A method of making a wafer level chip scale package, comprising:

• providing a temporary wafer level substrate;
• forming a wafer level interconnect structure over the temporary wafer level substrate using wafer level processes that include forming a first insulating layer over a top surface of the temporary wafer level substrate, and forming a first conductive layer over the first insulating layer;
• mounting a first semiconductor die over the wafer level interconnect structure in electrical contact with the first conductive layer;
• depositing a first encapsulant around the first semiconductor die;
• removing the temporary wafer level substrate to expose a bottom surface of the first insulating layer;
• and
• forming an interconnect structure in electrical contact with the first conductive layer.

A method of making a wafer level chip scale package, comprising:

• providing a temporary wafer level substrate;
• forming a wafer level interconnect structure over the temporary wafer level substrate using wafer level processes that include forming a first insulating layer on a top surface of the temporary wafer level substrate, and forming a first conductive layer over the first insulating layer;
• mounting a first semiconductor die over the wafer level interconnect structure in electrical contact with the first conductive layer;
• and
• depositing a first encapsulant around the first semiconductor die.

A semiconductor device, comprising:

• a temporary wafer level substrate;
• a wafer level interconnect structure disposed over the temporary wafer level substrate, the wafer level interconnect structure including a first insulating layer disposed over a top surface of the temporary wafer level substrate, and a first conductive layer disposed over the first insulating layer;
• a first semiconductor die disposed over the wafer level interconnect structure and in electrical contact with the first conductive layer;
• and
• a first encapsulant disposed around the first semiconductor die.